Abstract:
Antimonide-based III-V materials are highly interested in the channel of low power and high-speed
all-antimonide CMOS digital logic devices.
In this thesis work InGaSb-based double gate (DG) nMOSFET architectures with DG-nMOSFET
are proposed and numerically simulated. To assess and hence to compare the ballistic performance of
DG-JnMOSFET and, non-equilibrium greens function method is utilized under the framework of
well-known SILVACO’s ATLAS device simulation package without taking into account of
scattering. Wave function penetration to the oxide is taken into account in the simulation. In this
study the effect of gate length on drain current and other logic figures of merit like subthreshold
slope (SS), ION, IOFF, and ION/IOFF are investigated. The results obtained for DG-nMOSFET
demonstrate that there is negligible dependence on the “ON” current with the gate length. Small
increase in the OFF current is found for decreasing gate length from 15 nm to 13 nm, however, the
OFF current increases significantly when the gate length decreases from 13 nm. Subthreshold slope
decreases with increasing gate length. The maximum subthreshold swing is evaluated 80 mV/decade
for the gate length 7nm, which reduces to 70 mV/decade for the gate length 15 nm. Also the
threshold voltage decreases with decreasing gate length. Effect of the gate oxides (Al2O3 and HfO2)
in same equivalent oxide thickness (EOT) is also studied. The shift in threshold voltage and change
in ION/IOFF are found strong dependence with gate oxides having different dielectric constants.
Further, the effect of gate underlap is analyzed for the gate lengths 10nm and 15nm with different
underlap lengths. Drain current found to vary significantly for different underlap lengths when gate
length is 10nm. However, for the gate length 15 nm the variation of drain current is insignificant with
underlap length. The threshold voltage is also found to have strong dependence with gate length and
gate underlap length.
Description:
This thesis is submitted to the Department of Electrical and Electronic Engineering, Khulna University of Engineering & Technology in partial fulfillment of the requirements for the degree of Master of Science in Electrical and Electronic Engineering, December 2015.
Cataloged from PDF Version of Thesis.
Includes bibliographical references (pages 51-57).