Theoretical Performance of MOSFET with Graphene Channel

Abstract

The electronics components are becoming progressively smaller, gate scaling process has become saturated and the limits to Moore's Law are frequently considered. To overcome the difficulties of downscaling problems new structures and materials have been studied. The discovery of graphene has gained tremendous attention as the most promising materials for high speed electronic devices. Graphene, a flat mono layer of sp2 carbon atoms tightly packed into a two-dimensional (21)) honeycomb lattice, has recently attracted broad attention for future electronic device applications because of their excellent electronic characteristics such as high carrier mobility and high saturation velocity. The novel electronic properties of graphene lead to intense research into possible applications of this material in field effect transistors and nano scale devices. In this thesis, the performance of a graphene MOSFET is analyzed in large area and ballistic limit. The performance of a dual-gated large area graphene MOSFET is analyzed using analytical approach. The quantum transport simulation based on the NEGF formalism is used to analyze the performance of a top-gated graphene MOSFET in ballistic limit. The NEGF formalism is self-consistently coupled to the 1D Poisson equations. The Poisson equation is solved in 1D coordinate using the finite difference method (FDM). In large area dual gate graphene MOSFET, we have calculated sheet charge density dependent quantum capacitance self consistently considering charged impurities in the gate oxide layer. It is observed that with increasing. It is observed that with increasing charged impurities concentration the quantum capacitance increases near the Dirac point due to the limited density of states.With increasing the value of impurities concentration in the gate oxide layer,the minimum value of the quantum capacitance is also increased. Ultimately quantum capacitance is controlling the gate capacitance as well as the sheet charge density of graphene channel. A quasi-saturation of drain current called "kink" is observed in the output characteristics of both in large area and ballistic graphene MOSFET. This behaviour occurs due to the ambipolar nature of graphene channel. An ambipolar behavior occurs for a change in the conduction type at the drain end of the channel from p-type to n-type is clearly shown in transfer characteristics. Such a behavior is specific for G-MOSFETs, caused by the gapless nature of the channel due to the zero bandgap, and does not occur in conventional field effect transistors. The variation of sheet charge density with channel length at different drain bias (VdS) is also shown. As Vds is decreased negatively the corresponding sheet charge density decreases up to dirac point. After dirac point we obtain a positive gate to channel voltage at drain end which gives rise to an accumulation of electrons and corresponding increase in sheet charge density. The carrier drift velocity is increasing linearly with electric field but at a electric field of E=75.06 kY/cm, carrier drift velocity saturates to the average Fermi velocity of 2.12x 107cms-1. In ballistic graphene MOSFET, The IN characteristics shows standard MOSFET type behavior along with the high drain current current density reaching to approximately 12,000 µA/µm which is promising. The reason for the high current density can be attributed to the light effective mass of graphene and high carrier velocity. At lower gate voltage, a pronounced 'kink' is observed in drain current characteristics. At higher gate voltage this 'kink' behavior almost disappears. With the help of transfer characteristics, it is noticed that the dirac point shifts when the drain-source voltage is varied. The dirac point voltage, VdIC shifts significantly towards right at positive drain bias where as Vdirac shifts slightly towards left at negative drain bias. Therefore, the shift of dirac point voltage Vdiac in positive drain bias is more prominent than negative drain bias. Also, the p-n assymetry in transfer characteristics is the signature of short channel effect. The output transconductance of the device is obtained in the range of = 4500 µS/ um which is very much promising for high speed nano transistors. The variation of output transconductance, gm with the channel length is also shown. It is found that drain transconductance decreases at longer channel length. But, as the channel length scales down to 50 nm, the drain transconductance (g) rises significantly due to electrostatic gate effect.