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Design and Implementation of Sampling Rate Conversion System for Electroencephalogram (EEG) on FPGA Device

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dc.contributor.advisor Islam, Prof. Dr. Sheikh Md. Rabiul
dc.contributor.author Hassan, Mahamudul
dc.date.accessioned 2019-03-10T10:33:49Z
dc.date.available 2019-03-10T10:33:49Z
dc.date.copyright 2018
dc.date.issued 2018-11
dc.identifier.other ID 1409552
dc.identifier.uri http://hdl.handle.net/20.500.12228/499
dc.description This thesis is submitted to the Department of Electronics and Communication Engineering, Khulna University of Engineering & Technology in partial fulfillment of the requirements for the degree of Master of Science in Engineering in Electronics and Communication Engineering, November 2018. en_US
dc.description Cataloged from PDF Version of Thesis.
dc.description Includes bibliographical references in each chapter.
dc.description.abstract The wide scale use of digital communication and digital media has made the necessity of methods to process digital data more important now-a-days. The signal-rate system in digital signal processing has evolved the key of fastest speed in digital signal processor. Field Programmable Gate Array (FPGA) offers good solution for addressing the needs of high-performance DSP systems. This concept leads to a chip with attractive features like, low requirements for the coefficient word lengths, significant saving in computation and storage requirements results in a significant reduction in its dynamic power consumption. There are many algorithms have been proposed for processing of biomedical signal. Main objectives of these algorithm are to minimize noise and artifacts existing with these signals, so that it will be easy to analyze and diagnosis human diseases. The proposed system has many advantages on signal processing such that it has a simple structure, stationary response and adaptively with embedded microprocessors. The system is proposed due to facilitate structural characteristic and design properties on filtering EEG signal. The focus of this project is on the basic DSP functions, namely filtering signals to remove unwanted frequency using Sampling Rate Conversion (SRC) in digital signal processing. The system has a computer where the design can be programmed and simulated on Xilinx @ Integrated Software Environment (ISE) Suite 14.7 or Quartus II software with interface ALTRA Cyclone DE II board of FPGA device. en_US
dc.description.statementofresponsibility Mahamudul Hassan
dc.format.extent 75 pages
dc.language.iso en_US en_US
dc.publisher Khulna University of Engineering & Technology (KUET), Khulna, Bangladesh en_US
dc.rights Khulna University of Engineering & Technology (KUET) thesis/dissertation/internship reports are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission.
dc.subject Sampling Rate Conversion (SRC) en_US
dc.subject Digital Signal Processing en_US
dc.subject Electroencephalogram (EEG) Signal en_US
dc.title Design and Implementation of Sampling Rate Conversion System for Electroencephalogram (EEG) on FPGA Device en_US
dc.type Thesis en_US
dc.description.degree Master of Science in Engineering in Electronics and Communication Engineering
dc.contributor.department Department of Electronics and Communication Engineering


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